1. Field of the Invention
The present invention relates to emulation systems employing programming logic devices and other resources for emulating the behavior of an electronic circuit, and in particular to a hierarchical emulation system in which emulation resources communicate with one another via packets sent through a packet routing network.
2. Description of Related Art
A typical digital integrated circuit (IC) employs register transfer logic (RTL) wherein each block of logic within the IC includes an output register for synchronizing state changes in its output signals to edges of a clock signal. Typically a designer will first generate an RTL level, hardware description language (HDL) netlist employing Boolean expressions to characterize each block of logic, and will then employ a synthesis tool to convert the high level netlist into a gate level HDL netlist describing the logic blocks as sets of interconnected cells, where each cell is a standard IC component such as a transistor or a logic gate. The gate level netlist references each cell instance to be included in the IC by referring to an entry for that cell type in a cell library, a database including an entry for each kind of cell that can be included in an IC. The cell library entry for each cell type includes a model of the cell's behavior that circuit simulation and verification tools can employ. After creating the gate level netlist, the designer employs a placement and routing (P&R) tool to convert the gate level netlist into an IC layout file indicating the position and layout within a semiconductor die of each cell forming the IC and describing how the nets are to be routed between cell terminals. The layout file guides fabrication of the IC.
An IC designer usually employs computer-aided simulation and verification tools at each step of the design process to verify that the IC will behave as expected. To do so, the designer may develop a “testbench” for a computer-based circuit simulator incorporating the netlist describing the IC “device under test” (DUT) to be simulated and indicating how the DUT's input signals are to change state over time. The testbench will also list various signals of the DUT to be monitored during the simulation including test signals and signals the DUT generates in response to the test signals. The simulator creates a behavioral model of the DUT based on the testbench description of the DUT and on-behavioral models of the DUT's cells obtained from the cell library and then tests the DUT model to determine how the monitored signals would respond to input signal patterns the testbench describes. During the test, the simulator generates a “dump file” containing waveform data representing the time-varying behavior of the monitored signals. The designer can then use various debugging tools to inspect the dump file to determine whether the DUT behaved as expected.
Although a simulator can accurately model the behavior of an IC based on either an RTL level or gate level netlist, it can require much processing time to simulate IC behavior. To reduce simulation time a designer can program a simulator to simulate only those portions of an IC design that are new or have been modified, but this approach may not provide any assurance that the new and old portions of the design will work properly together.
One way to reduce the time needed to verify the DUT logic a netlist describes is to use programmable logic devices to emulate the DUT logic. For example U.S. Pat. No. 6,377,911 issued Apr. 23, 2002 to Sample et al, describes a logic emulation system employing field programmable gate arrays (“FPGAs”) that can be programmed to emulate DUT logic. Since the FPGAs employ logic gates rather than software to emulate circuits, emulation using FPGAs can be much quicker than simulation.
FIG. 1 illustrates a typical prior art emulation system 10 including a set of circuit boards 12 each holding an array of FPGAs 14, each of which can be programmed to emulate the logic of a large number of interconnected logic gates, flip-flops and registers. Each FPGA 14 has many I/O terminals and some of those I/O terminals are linked to I/O terminals of other FPGAs 14 on the same circuit board 12 so that the FPGAs can communicate with one another. Circuit boards 12 reside in slots on a motherboard 15 including a backplane for interconnecting I/O terminals of FPGAs 14 residing on different circuit boards 12 so that they too can communicate with one another. In some systems the signal paths between FPGAs or FPGA boards are linked via programmable routing devices such as crosspoint switches to provide more flexible signal routing between FPGAs. A conventional workstation 16 processes the user's netlist description of the DUT to produce a set of instructions for programming FPGAs 14 to emulate DUT logic and transmits those instructions to programming inputs of FPGA 14 via one or more input/output (I/O) interface cards 17 installed in a slot of the PCI bus of workstation 16. Each I/O interface card 17 is capable of transmitting signals to and receiving signals from resources mounted on motherboard 15 via signal paths motherboard 15 provides.
In addition to logic FPGAs 14 can emulate, ICs may include large standardized components such embedded computer processors and memories that can be emulated by processors or memory ICs mounted on “resource boards” 18 that may also be installed in slots of motherboard 15. Backplane wiring on motherboard 15 links terminals of the devices mounted on resource boards 18 to I/O terminals of various FPGAs 14 mounted on FPGA boards 12.
A designer normally intends an IC to be installed on a circuit board of an external system so that it can communicate with other devices within that system. When emulator 10 is to act as an in-circuit emulation (“ICE”) system, the emulator includes an external system interface circuit 22 providing signal paths between I/O terminals of FPGAs 14 and a socket of the external system 24 of the type in which the IC being emulated will eventually reside. A cable 27 interconnects interface 22 with external system 24 and typically includes a connector that fits into the IC socket.
Emulation system 10 may also include pattern generation and data acquisition circuits 26 mounted on circuit boards installed in motherboard 15 and linked through signals paths on the motherboard to I/O terminals of FPGAs 14. These circuits supply input signals to the FPGAs and monitor selected FPGA output signals during the emulation process to acquire “probe data” representing the behavior of the DUT output signals. Following the emulation process, a user may employ debugging software to analyze the probe data to determine whether the DUT will behave as expected.
FIG. 2 illustrates an alternative prior art emulator architecture 20 wherein resource cards 28 mounted in slots accessing the memory bus of a workstation 33 emulation some portions of a DUT while workstation 33 emulates other portions of the DUT. Each card 28 includes an array of interconnected FPGAs 14 and may include other resources 30 such as memories linked to I/O terminals of FPGAs 14. An I/O interface circuit 32 in each card 28 includes I/O terminals connected to many I/O terminals of FPGAs 14. Workstation 33 sends instructions via its PCI bus to an I/O interface circuit 32 on each card 28 telling it how to configure FPGAs for to emulate circuit logic.
As mentioned above, a testbench is a program for a circuit simulator describing an IC device under test (DUT) also describes the test signal inputs to the DUT and indicates which of the DUT's input and output signals are to be monitored. FIG. 18 is a conceptual block diagram illustrating how an emulation system would implement the various functions of a testbench including a generator 34, a transactor 35, the DUT 36 and a monitor 37. FPGAs programmed and interconnected to emulate an IC described by a netlist typically form the emulated DUT 36. The “generator” 34 is relatively high level software code that the IC designer writes to describe the test signals to be supplied as input to DUT 36. For example a portion of generator code might appear as follows:    write location1 data1
The word “write” is a command indicating the value of a variable data1 is to be written to DUT input terminal (s) a variable location1 identifies. The IC designer would typically write this line of code. “Transactor” 35 is the equipment needed to implement the generator's high-level commands. For example the transactor 35 would respond to the write command by setting an input signal or signals at the DUT input identified by “locations” to the value of “data1”. “Monitor” 37 is the equipment needed to monitor DUT input and output signals during the emulation.
While emulators typically use FPGAs and other hardware to emulate DUT 36, they may use either of two approaches to handling the functions of generator 34, transactor 35 and monitor 37. In the emulation system 10 of FIG. 1, specialized pattern generation and data acquisition circuits 26 that may or may not reside on motherboard 15 can carry out all of these testing functions, and it is necessary to program these devices to supply test signal patterns as inputs to DUT 36 and to monitor DUT output signals by sampling them at appropriate times during the emulation process and storing data representing the DUT output signal states. One difficulty with this approach, in addition to requiring specialized test equipment 26, is that it is necessary to translate the portions of the testbench relating to generator 34 and monitor 37 into program instructions for the test equipment.
In the emulation system 20 of FIG. 2, workstation 33 and I/O interface devices 32 carry out all of the functions of generator 34, transactor 35 and monitor 37. Software running on workstation entirely implements generator 34. Software running on workstation 33 and I/O interface devices 32 jointly implement transactor 35 and monitor 37. This approach avoids the need to program specialized test equipment, but will normally require a reduction in the frequency at which DUT 36 can operate during the emulation because workstation 33 typically will not be able to communicate with the DUT 36 via I/O interface circuit 32 at sufficiently high signal frequencies.
One additional drawback to both emulation systems 10 and 20 is that they are not highly scalable since the number of slots in motherboard 15 and the number of bus slots in workstation 16 limit the number of FPGAs and other resources they can provide.